This week on the IEEE Electronic Components and Packaging Technology Conference, Intel unveiled that it’s creating new chip packaging expertise that may enable for greater processors for AI.
With Moore’s Regulation slowing down, makers of superior GPUs and different information middle chips are having so as to add extra silicon space to their merchandise to maintain up with the relentless rise of AI’s computing wants. However the most measurement of a single silicon chip is fastened at round 800 sq. millimeters (with one exception), in order that they’ve needed to flip to advanced packaging technologies that combine a number of items of silicon in a means that lets them act like a single chip.
Three of the improvements Intel unveiled at ECTC had been geared toward tackling limitations in simply how a lot silicon you may squeeze right into a single bundle and the way large that bundle might be. They embody enhancements to the expertise Intel makes use of to hyperlink adjoining silicon dies collectively, a extra correct technique for bonding silicon to the bundle substrate, and system to broaden the scale of a essential a part of the bundle that take away warmth. Collectively, the applied sciences allow the mixing of greater than 10,000 sq. millimeters of silicon inside a bundle that may be greater than 21,000 mm2—a large space concerning the measurement of 4 and a half credit cards.
EMIB will get a 3D improve
One of many limitations on how a lot silicon can slot in a single bundle has to do with connecting numerous silicon dies at their edges. Utilizing an natural polymer bundle substrate to interconnect the silicon dies is probably the most reasonably priced possibility, however a silicon substrate means that you can make extra dense connections at these edges.
Intel’s resolution, launched greater than 5 years in the past, is to embed a small sliver of silicon within the natural bundle beneath the adjoining edges of the silicon dies. That sliver of silicon, referred to as EMIB, is etched with high quality interconnects that enhance the density of connections past what the natural substrate can deal with.
At ECTC, Intel unveiled the most recent twist on the EMIB expertise, referred to as EMIB-T. Along with the standard high quality horizontal interconnects, EMIB-T gives comparatively thick vertical copper connections referred to as through-silicon vias, or TSVs. The TSVs enable energy from the circuit-board under to immediately connect with the chips above as an alternative of getting to route across the EMIB, decreasing energy misplaced by an extended journey. Moreover, EMIB-T incorporates a copper grid that acts as a floor aircraft to cut back noise within the energy delivered because of course of cores and different circuits immediately ramping up their workloads.
“It sounds easy, however it is a expertise that brings quite a lot of functionality to us,” says Rahul Manepalli, vp of substrate packaging expertise at Intel. With it and the opposite applied sciences Intel described, a buyer might join silicon equal to greater than 12 full measurement silicon dies—10,000 sq. millimeters of silicon—in a single bundle utilizing 38 or extra EMIB-T bridges.
Thermal management
One other expertise Intel reported at ECTC that helps enhance the scale of packages is low-thermal-gradient thermal compression bonding. It’s a variant of the expertise used at the moment to connect silicon dies to natural substrates. Micrometer-scale bumps of solder are positioned on the substrate the place they are going to connect with a silicon die. The die is then heated and pressed onto the microbumps, melting them and connecting the bundle’s interconnects to the silicon’s.
As a result of the silicon and the substrate broaden at completely different charges when heated, engineers need to restrict the inter-bump distance, or pitch. Moreover, the growth distinction makes it troublesome to reliably make very giant substrates stuffed with a lot of silicon dies, which is the route AI processors must go.
The brand new Intel tech makes the thermal growth mismatch extra predictable and manageable, says Manepalli. The result’s that very-large substrates might be populated with dies. Alternatively, the identical expertise can be utilized to extend the density of connections to EMIB all the way down to about one each 25 micrometers.
A flatter warmth spreader
These greater silicon assemblages will generate much more warmth than at the moment’s methods. So it’s essential that the warmth’s pathway out of the silicon isn’t obstructed. An built-in piece of steel referred to as a warmth spreader is vital to that, however making one sufficiently big for these giant packages is troublesome. The bundle substrate can warp and the steel warmth spreader itself may not keep completely flat; so it may not contact the tops of the new dies it’s purported to be sucking the warmth from. Intel’s resolution was to assemble the built-in warmth spreader in elements as an alternative of as one piece. This allowed it so as to add additional stiffening elements amongst different issues to maintain all the pieces in flat and in place.
“Retaining it flat at increased temperatures is an enormous profit for reliability and yield,” says Manepalli.
Intel says the applied sciences are nonetheless within the in R&D stage and wouldn’t touch upon when these applied sciences would debut commercially. Nonetheless, they are going to possible need to arrive within the subsequent few years for the Intel Foundry to compete with TSMC’s planned packaging expansion.
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