This can be a sponsored article dropped at you by Siemens.
Layout versus schematic (LVS) comparison is a crucial step in integrated circuit (IC) design verification, ensuring that the physical layout of the circuit matches its schematic representation. The primary goal of LVS is to verify the correctness and functionality of the design. Traditionally, LVS comparison is performed during signoff verification, where dedicated tools compare layout and schematic data to identify any inconsistencies or errors. However, uncovering errors at the signoff stage leads to time-consuming iterations that delay design closure and time to market. While early-stage LVS comparison could mitigate these issues, it often generates millions of error results due to the incomplete status of the design.
To address these challenges, we developed a shift-left methodology, allowing designers to perform LVS comparison earlier in the design flow. By incorporating LVS checks at earlier stages, design teams can catch errors sooner and reduce the number of iterations required during signoff. Let’s take a deeper look at how a shift-left LVS verification approach can enhance designer productivity and accelerate verification.
The Calibre nmLVS™ Recon Evaluate resolution introduces an clever shift-left course of for quick and exact LVS comparability earlier within the design cycle. It automates the black boxing of incomplete blocks and facilitates computerized port mapping, permitting designers to attain sooner LVS iterations on early-stage designs.
Challenges of conventional LVS verification
Within the conventional LVS verification course of, designers should confirm the format towards its schematic illustration to make sure that the ultimate product capabilities as meant. As a result of all design blocks have to be accomplished and prepared for ultimate comparability, verification groups wait till signoff levels to carry out thorough checks. Any errors found throughout this late-stage LVS run can set off further verification iterations, resulting in wasted time and sources. Designers are then caught in a cycle of re-running the LVS course of every time a repair or replace is carried out, leading to a bottleneck throughout signoff.
Designers may run LVS evaluate earlier, though within the early levels of design many blocks should not but finalized, making a complete LVS comparability impractical. Operating LVS on incomplete designs can generate tens of millions of error messages, a lot of which aren’t actionable as a result of they originate from the uncompleted parts of the format. This overwhelming variety of outcomes makes it tough to pinpoint precise design points, rendering conventional LVS strategies impractical for early-stage verification.
As proven in determine 1, the verification movement may be extra advanced when design blocks are accomplished at completely different instances, driving a number of iterations of verification checks as every block is built-in into the general format.
Fig. 1: Design verification cycle with blocks at completely different ranges of completion.
Shifting left for early LVS verification
Implementing a shift-left methodology for LVS verification means performing format vs. schematic comparisons earlier within the design cycle, earlier than all blocks are finalized. To allow this, the movement should help flexibility in coping with incomplete designs and permit for extra focused verification of vital blocks and connections.
One strategy to obtain that is by way of automation strategies like black boxing and port mapping. By abstracting the interior particulars of incomplete blocks whereas preserving their exterior connectivity info, the verification movement may be tailor-made to give attention to interactions between accomplished and incomplete sections of the design. Automated port mapping, however, ensures that each one exterior connections between format and schematic are appropriately aligned for correct early-stage comparisons.
A brand new method to early LVS verification
A sophisticated methodology for early-stage LVS verification leverages these automated processes to speed up the shift-left verification course of. As an illustration, clever black boxing of incomplete blocks can considerably scale back the variety of error outcomes generated, making it simpler for verification groups to determine precise connectivity points between blocks.
The shift-left movement additionally advantages from using a robust comparability engine that may analyze format and schematic information shortly and effectively, skipping pointless operations and calculations. This method focuses on the toughest issues early within the movement, leading to fewer errors found on the signoff stage and in the end rushing up design closure.
The flows illustrated in determine 2 exhibits how this shift-left methodology streamlines the verification course of by decreasing pointless steps and specializing in vital design points.
Fig. 2: The normal full LVS movement with all steps (left) vs. the Calibre nmLVS Recon movement (proper).
Benefits of early LVS evaluate
Adopting a shift-left methodology for LVS verification provides a number of key advantages to semiconductor design groups:
Early detection of errors: By performing LVS comparisons earlier within the design movement, errors may be recognized and resolved earlier than they turn into deeply embedded within the design. This proactive method reduces the danger of pricey rework and minimizes the variety of iterations wanted throughout signoff.
Accelerated design verification: Automating the comparability course of streamlines design verification, permitting designers to determine and resolve points effectively, even when all blocks should not finalized. This results in sooner total circuit verification and reduces the effort and time required for guide inspection.
Improved collaboration and debugging: With a centralized platform for verifying design correctness and sharing suggestions, early-stage LVS verification promotes collaboration throughout design groups. Engineers can isolate points extra successfully and supply insights to their colleagues, enhancing total design high quality.
Elevated design confidence: Making certain alignment between format and schematic representations from the early levels of design boosts confidence within the ultimate product’s correctness. By the point the design reaches signoff, a lot of the vital connectivity points have already been resolved.
Actual-world purposes
Calibre nmLVS Recon has demonstrated important advantages in actual design initiatives, together with 10x runtime enhancements and 3x decrease reminiscence necessities. A verification crew at Marvell, for instance, enhanced their LVS movement over the total design cycle utilizing Calibre nmLVS SI, reaching sooner verification instances and improved effectivity.
Conclusion
Shifting LVS evaluate duties earlier into the design movement provides important advantages to IC design groups. Our novel method to early top-level LVS comparability automates black boxing and port mapping so designers can carry out complete verification even when all blocks should not finalized. This accelerates design verification, improves collaboration, and enhances design confidence in semiconductor design workflows.
Be taught extra by downloading my latest technical paper “Accelerate design verification with Calibre nmLVS Recon Compare.”
